Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, such as an electrical charge or voltage, which represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.
Some memory devices, commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states.
Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.
Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate”, Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.
Analog memory cells are often programmed using Program and Verify (P&V) processes. In a typical P&V process, a cell is programmed by applying a sequence of voltage pulses, whose voltage level increases from pulse to pulse. The programmed voltage level is read (“verified”) after each pulse, and the iterations continue until the desired level is reached.
Various methods for increasing the speed of memory device programming are known in the art. For example, U.S. Pat. No. 7,177,200, whose disclosure is incorporated herein by reference, describes a method that initially programs a Flash memory device in a quick manner that produces relatively broad threshold voltage distributions, which would render the flash memory unreliable in the long term if left uncorrected. Then, while the host of the memory device is idle, the memory device shifts and tightens up its threshold voltage distributions sufficiently to obtain long-term reliability.
U.S. Patent Application Publication 2002/0118574, whose disclosure is incorporated herein by reference, describes a programming method, which programs each cell to its target state using a data-dependent programming voltage. In some embodiments, the programming operation is performed in multiphase wherein each successive phase is executed with a finer programming resolution, such as by employing a programming voltage with a gentler staircase waveform.
U.S. Pat. No. 6,301,151, whose disclosure is incorporated herein by reference, describes an adaptive programming method for Flash memory analog storage. The voltage of a programming pulse is adjusted based on the result of the previous pulse. The expected change in the programmed value is compared to the measured change, and the difference used to improve the model of that cell after each programming pulse.
U.S. Patent Application Publication 2006/0285396, whose disclosure is incorporated herein by reference, describes a programming process, which increases the programming voltage of successive programming cycles in relation to the percentage of the data bits that failed programming verification during the previous programming cycle and were not correctly programmed into the memory array.